Bi-directional esd protection circuit

ABSTRACT

A structure is designed with an external terminal ( 100 ) and a reference terminal ( 102 ). A first transistor ( 106 ) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor ( 118 ) has a current path coupled between the external terminal and the substrate. A third transistor ( 120 ) has a current path coupled between the substrate and the reference terminal.

FIELD OF THE INVENTION

This invention relates to an integrated circuit and more particularly toa bi-directional protection circuit.

BACKGROUND OF THE INVENTION

Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS(BiCMOS) circuits employ electrostatic discharge protection (ESD)circuits to protect against electrostatic discharge due to ordinaryhuman and machine handling. This electrostatic discharge occurs when thesemiconductor circuit contacts an object that is charged to asubstantially different electrostatic potential of typically severalthousand volts. The contact produces a short-duration, high-currenttransient in the semiconductor circuit. This high current transient maydamage the semiconductor circuit through joule heating. Furthermore,high voltage developed across internal components of the semiconductorcircuit may damage MOS transistor gate oxide.

Sensitivity of the semiconductor circuit is determined by various testmethods. A typical circuit used to determine sensitivity of thesemiconductor circuit to human handling includes a capacitor andresistor that emulate a human body resistor-capacitor (RC) timeconstant. The capacitor is preferably 100 pF, and the resistor ispreferably 1500Ω, thereby providing a 150-nanosecond time constant. Asemiconductor device is connected to the test circuit at a predeterminedexternal terminal for a selected test pin combination. In operation, thecapacitor is initially charged to a predetermined stress voltage anddischarged through the resistor and the semiconductor device. Thispredetermined stress voltage preferably includes both positive andnegative stress voltages with respect to a reference pin or terminal. Apost stress current-voltage measurement determines whether thesemiconductor device is damaged. Although this test effectively emulateselectrostatic discharge from a human body, it fails to comprehend othercommon forms of electrostatic discharge.

A charged-device ESD test is another common test method for testingsemiconductor device sensitivity. This method is typically used todetermine sensitivity of the semiconductor circuit to ESD underautomated manufacturing conditions. The test circuit includes a stressvoltage supply connected in series with a current limiting resistor. Thesemiconductor device forms a capacitor above a ground plane that istypically 1-2 pF. A low impedance conductor forms a discharge pathhaving an RC time constant typically two orders of magnitude less than ahuman body model ESD tester. In operation, the semiconductor device isinitially charged with respect to the ground plane to a predeterminedstress voltage. The semiconductor device is then discharged at aselected terminal through the low impedance conductor. This connectionproduces a high-voltage, high-current discharge in which a magnitude ofthe initial voltage across the semiconductor device approaches that ofthe initial stress voltage.

A particular protection circuit design problem arises when protectioncircuits are connected to an external terminal that receives bothpositive and negative voltages with respect to a reference terminal suchas V_(SS) during normal circuit operation. Many analog and mixed signalcircuits must accommodate such positive and negative signal voltageswings. These signal voltage swings will turn on conventionaltransistors during normal circuit operation. These positive and negativevoltage swings, therefore, preclude a use of many conventionalprotection circuit devices. Furthermore, the protection circuits ofanalog and mixed signal circuits must conduct current in a low impedancestate in response to an external ESD pulse. They must also remain in ahigh impedance state during normal circuit operation, and they mustprotect against positive and negative ESD pulses outside of normaloperating parameters as well.

Referring now to FIG. 4, there is a dual silicon-controlled-rectifier(SCR) circuit of the prior art. This dual SCR circuit includes SCRcircuits 406 and 408 connected between external terminal or bond pad 400and reference terminal 410. The SCR circuits are arranged in parallelwith opposite polarities. Thus, SCR 406 has an anode connected toexternal terminal 400 and a cathode connected to reference terminal 410to conduct in response to positive ESD pulses at external terminal 400.SCR 408 has a cathode connected to external terminal 400 and an anodeconnected to reference terminal 410 to conduct in response to negativeESD pulses at external terminal 400. These circuits offer limitedflexibility in adjustment of trigger voltage thresholds. They aretypically activated by a PN junction avalanche threshold voltage inresponse to a relatively high voltage ESD pulse. This high voltage ESDpulse may damage thin oxide devices in protected circuit 404 prior toactivating either SCR. These circuits have a further disadvantage thattwo of them are required for bi-directional operation in response toboth polarities of ESD stress.

SUMMARY OF THE INVENTION

These problems are resolved by a structure with an external terminal anda reference terminal. The structure includes a first transistor formedon a substrate. The first transistor has a current path coupled betweenthe external terminal and the reference terminal. A second transistorhas a current path coupled between the external terminal and thesubstrate. A third transistor has a current path coupled between thesubstrate and the reference terminal.

The present invention provides bi-directional ESD protection forpositive and negative operating voltages. Circuit area is conserved by asingle primary protection device.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the invention may be gained by readingthe subsequent detailed description with reference to the drawingswherein:

FIG. 1A is a schematic diagram of a protection circuit of the presentinvention using MOS transistors;

FIG. 1B is a layout diagram of the protection circuit of FIG. 1A;

FIG. 1C is a cross section diagram of the protection circuit of FIG. 1Btaken at A-A;

FIG. 2A is a schematic diagram of another embodiment of the protectioncircuit of the present invention;

FIG. 2B is a layout diagram of the protection circuit of FIG. 2A;

FIG. 3 is a schematic diagram of yet another embodiment of theprotection circuit of the present invention;

FIG. 4 is a schematic diagram of a bi-directional protection circuit ofthe prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1A, there is a schematic diagram of a protectioncircuit of the present invention using a metal oxide semiconductor (MOS)transistor 106 as a primary protection device. This MOS transistor 106has a current path connected between bond pad or external terminal 100and reference terminal 102. A control gate of the MOS transistor 106 iscoupled to a substrate or bulk terminal via lead 108. The substrateterminal is connected to a common terminal of current paths of MOStransistors 118 and 120. These MOS transistors are preferably about 30micrometers wide for an on resistance of about 1 kΩ. A resistor 114couples another end of the current path of transistor 118 to bond pad100. A similar resistor 116 couples another end of the current path oftransistor 120 to reference terminal 102. Both these resistors 114 and116 are preferably about 1 kΩ each. A control gate of transistor 118 isconnected to a common terminal of transistor 120 and resistor 116.Another control gate of transistor 120 is connected to a common terminalof transistor 118 and resistor 114. The bond pad 100 is connected toprotected circuit 188.

The layout of the protection circuit of FIG. 1A will now be explained indetail with reference to FIG. 1B and the cross section diagram of FIG.1C at A-A. Reference numerals of these figures correspond to comparablereference numerals of FIG. 1A. The layout of FIG. 1B includes MOStransistors 106, 118 and 120 formed on P-substrate 172 within lightlydoped P-well region 171. A heavily doped N+ diffusion under field (DUF)170 underlies the P-well region 171. This DUF 170 is preferably about4-6 micrometers thick and about 3-4 micrometers below the siliconsubstrate surface. The P-well region 171 is enclosed by lightly dopedN-well region 104. This N-well region 104 extends from a face into thesubstrate to make electrical contact with the underlying DUF 170,thereby electrically isolating P-well region 171 from the rest of theP-substrate 172. The N-well region 104 indicated by the dashed line(FIG. 1A) is electrically contacted by N+ doped region 156 and overlyingfirst metal stripe 111 designated by a dotted fill pattern. This N+doped region is preferably 0.3-0.4 micrometers thick. The N+ dopedregion 156 and first metal stripe 111 are electrically connected bycontact areas 158 designated by a solid fill pattern. The metal stripe111 is preferably connected to a positive supply voltage terminal.

The MOS transistor 106 includes plural alternating drain 180 and sourceregions 182 with intervening control gate regions 126. Common drain andsource regions are connected to respective first metal stripes 163 and164 by contacts 160 and 162. Each first metal drain stripe is connectedto a second metal bus 150 by vias 128 indicated by a cross fill pattern.The second metal bus 150 is further connected to the bond pad orexternal terminal 100. Each first metal source stripe is connected to asecond metal bus 152 by vias 129 and to V_(SS) reference supply terminal102. The control gate 126 of MOS transistor 106 is connected to P+region 132 by first metal 108 and respective contacts. This P+ region132 electrically connects the control gate 126 to the P-well region 171.First metal region 108 further connects P+ region 132 to N+ region 144at a common current path terminal between transistors 118 and 120. Thecurrent path terminal 142 of transistor 120 is connected by first metallead 122 to polycrystalline silicon resistor 116 and to the control gateof transistor 118. Polycrystalline silicon resistor 116 is furtherconnected and to reference terminal 152 by lead 112. The current pathterminal 140 of transistor 118 is connected by first metal lead 124 topolycrystalline silicon resistor 114 and to the control gate oftransistor 120. Polycrystalline silicon resistor 114 is connected and tobond pad 150 by lead 110.

In normal circuit operation when there is no ESD pulse, the protectioncircuit, including MOS transistor 106, is designed to remain in a highimpedance state. When a voltage at bond pad 100 is more than one MOStransistor threshold voltage (V_(T)) positive with respect to referenceterminal 102, transistor 118 is off. The voltage at lead 124, therefore,is the same as at bond pad 100, and transistor 120 is on. In this onstate, transistor 120 holds lead 108 to the voltage at referenceterminal 102. Thus, transistor 106 remains off. Alternatively, when avoltage at bond pad 100 is more than one V_(T) negative with respect toreference terminal 102, transistor 120 is off, and transistor 118 is on.In this on state, transistor 118 holds lead 108 to the voltage at bondpad 100. Thus, transistor 106 remains off. The on-resistance oftransistors 118 and 120 and respective series resistors 114 and 116 arechosen so that normal signal transitions at bond pad 100 do notcapacitively couple more than a diode drop or about 0.7 volts to thecommon gate-substrate lead 108. In the embodiment of FIG. 1A, resistors114 and 116 are formed from P+ doped polycrystalline silicon with asilicide blocking layer. The resistance of these resistors and the onresistance of each of transistors 118 and 120, therefore, is preferablyabout 1 kΩ each.

During ESD operation, application of a positive ESD pulse to bond pad100 with respect to reference terminal 102 capacitively couples apositive voltage via parasitic gate-drain capacitance (not shown) oftransistor 106 to lead 108. The positive transition of lead 108increases the voltage at P-well region 171 through P+ doped region 132.This positive voltage at leads 110 and 108 initiates a transition of theparasitic NPN bipolar transistor of MOS transistor 106 from BV_(CBO)(open emitter collector-base breakdown voltage) to BV_(CEO) (open basecollector-emitter breakdown) or snapback. In snapback, MOS transistor106, including the parasitic NPN transistor, conduct the ESD currentfrom bond pad 100 to reference terminal 102, thereby preventing anexcessive voltage increase that might otherwise damage protected circuit188. The ESD pulse at bond pad 100 also couples a voltage to lead 124and turns on transistor 120. The on resistance of transistor 120together with the series resistance of resistor 116, however, provide arelatively slow discharge of the gate capacitance of MOS transistor 106.The voltage coupled to lead 108, therefore, is not effectivelydischarged by transistor 120 until most of the ESD current has beendischarged.

Application of a negative ESD pulse to bond pad 100 with respect toreference terminal 102 has the same effect as application of a positiveESD pulse to reference terminal 102 with respect to bond pad 100.Furthermore, due to symmetry of the circuit of FIG. 1A and isolation ofthe P-well region 171 from P-substrate 172, the protection circuitoperates as previously described except for a change of polarity. Thenegative ESD pulse capacitively couples a negative voltage via parasiticgate-drain capacitance of transistor 106 to lead 108. The negativetransition of lead 108 decreases the voltage at P-well region 171through P+ doped region 132. This negative voltage at leads 110 and 108initiates a transition of the parasitic NPN bipolar transistor of MOStransistor 106 from BV_(CBO) to BV_(CEO) or snapback. In snapback, MOStransistor 106, including the parasitic NPN transistor, conduct the ESDcurrent from reference terminal 102 to bond pad 100. The ESD pulse atbond pad 100 also couples a negative voltage to lead 124 and turns ontransistor 118. The on resistance of transistor 118 together with theseries resistance of resistor 114 provide a relatively slow discharge ofthe gate capacitance of MOS transistor 106. The voltage coupled to lead108, therefore, is not effectively discharged by transistor 118 untilmost of the ESD current has been discharged.

This circuit is highly advantageous in providing ESD protection againstboth positive and negative ESD stress pulses. This bi-directionaloperation provides this ESD protection with a single MOS transistor 106as a primary protection device. This single device conserves layout areaand minimizes circuitry adjacent the bond pad. A further advantage ofthe present invention is the compatibility with both positive andnegative signal voltages at bond pad 100 during normal operation. Foreither polarity of signal voltage, the protection circuit, including MOStransistor 106, remains in a high impedance or nonconducting stateduring normal circuit operation.

Referring now to FIG. 2A, there is a schematic diagram of anotherembodiment of the protection circuit of the present invention and acorresponding layout diagram (FIG. 2A). This embodiment is the same asthe protection circuit of FIG. 1A except for the addition of diodes 196and 198. These diodes are formed by the addition of P+ heavily dopedregions respectively designated 196 and 198 within N-well region 104.These diodes 196 and 198 conduct ESD current to N-well region 104 andDUF region 170 under forward bias during respective positive andnegative ESD pulses at bond pad 100. For a positive ESD pulse at bondpad 100, for example, the ESD current increases a voltage at N-wellregion 104 and DUF region 170 with respect to reference terminal 102.This increased voltage is capacitively coupled to the enclosed P-wellregion 171 by means of the parasitic junction capacitance (not shown) ofreverse biased diode 186. This increase in voltage serves to forwardbias the emitter of the parasitic NPN transistor of MOS transistor 106,thereby initiating conduction of the protection circuit. Alternatively,application of a negative ESD pulse at bond pad 100 will decrease thevoltage at lead 110 and forward bias the emitter of the parasitic NPNtransistor of MOS transistor 106. Under forward bias, the base currentof the parasitic NPN transistor will charge the parasitic junctioncapacitance (not shown) of reverse biased diode 186. Initial conductionof the protection circuit, therefore, is enhanced by diodes 196 and 198for either polarity of ESD stress pulse. This is highly advantageous inlowering the trigger threshold of the protection circuit, therebylimiting the maximum voltage at protected circuit 188.

Turning now to FIG. 3, there is a schematic diagram of yet anotherembodiment of the protection circuit of the present invention. Thisembodiment is the same as the embodiment of FIG. 1A, except that NPNbipolar transistor 300 replaces MOS transistor 106. This NPN bipolartransistor 300 may be formed by individual N+ regions 180 and 182without intervening gate region 126 (FIG. 1A). Operation of theprotection circuit is the same as previously described for the parasiticNPN transistor of MOS transistor 106 in previous embodiments. A furtheradvantage of this embodiment, however, is that thin oxide regions areeliminated in the primary protection device. Elimination of these thinoxide regions greatly reduces a likelihood of gate dielectric damage dueto rapid ESD transients such as charged device stress.

Although the invention has been described in detail with reference toits preferred embodiments, it is to be understood that this descriptionis by way of example only and is not to be construed in a limitingsense. For example, various combinations of resistors and transistors ofthe previous embodiments may be combined to provide the advantages ofthe present invention as will be appreciated by one of ordinary skill inthe art having access to the instant specification. In particular, theembodiment of FIG. 3 may readily be combined with diodes 196 and 198 ofthe embodiment of FIG. 2A. Furthermore, the inventive concept of thepresent invention may be advantageously extended to many paralleltransistors 106 or 300 in a semiconductor body without current hogging.

It is to be further understood that numerous changes in the details ofthe embodiments of the invention will be apparent to persons of ordinaryskill in the art having reference to this description. It iscontemplated that such changes and additional embodiments are within thespirit and true scope of the invention as claimed below.

1-20. (canceled)
 21. A circuit, comprising: a first terminal; a secondterminal; a third terminal; a device having a current path coupledbetween the first and second terminals; a first transistor having acurrent path coupled between the first terminal and the third terminaland having a control terminal coupled to the second terminal; and asecond transistor having a current path coupled between the secondterminal and the third terminal and having a control terminal coupled tothe first terminal.
 22. A circuit as in claim 21, wherein the device andthe first and second transistors are formed at a face of a firstsemiconductor region having a first conductivity type.
 23. A circuit asin claim 22, wherein the first semiconductor region is surrounded on allsides by a second semiconductor region having a second conductivitytype.
 24. A circuit as in claim 22, wherein the first semiconductorregion is enclosed on all sides and below by a second semiconductorregion having a second conductivity type, and wherein the secondsemiconductor region is formed in a third region isolated from the firstregion.
 25. A circuit as in claim 21, wherein the device is an MOStransistor.
 26. A circuit as in claim 25, wherein the MOS transistorcomprises a control terminal coupled to the third terminal.
 27. Acircuit as in claim 25, wherein the current path of the first transistoris coupled between the first and third terminals by a first resistor andthe current path of the second transistor is coupled between the secondand third terminals by a second resistor.
 28. A circuit as in claim 25,wherein each of the MOS transistor, the first transistor, and the secondtransistor comprises a bulk terminal coupled to the third terminal. 29.A circuit as in claim 21, wherein the device is a bipolar transistor.30. A circuit as in claim 29, wherein the bipolar transistor comprises acontrol terminal coupled to the third terminal.
 31. A circuit as inclaim 30, wherein each of the first and second transistors comprises abulk terminal coupled to the third terminal.
 32. A circuit as in claim29, wherein the current path of the first transistor is coupled betweenthe first and third terminals by a first resistor and the current pathof the second transistor is coupled between the second and thirdterminals by a second resistor.
 33. A circuit as in claim 21, whereinthe device comprises a plurality of parallel elongate semiconductorregions having a first conductivity type, and wherein the current pathof the device comprises a plurality of semiconductor regions having asecond conductivity type formed between respective said semiconductorregions having the first conductivity type.
 34. A circuit, comprising: afirst terminal; a second terminal; a third terminal; a first devicehaving a current path coupled between the first and second terminals; asecond device having a current path coupled between the first terminaland the third terminal, the second device current path not conducting inresponse to a positive voltage at the first terminal with respect to thesecond terminal and conducting in response to the positive voltage atthe second terminal with respect to the first terminal; and a thirddevice having a current path coupled between the second terminal and thethird terminal, the third device current path conducting in response tothe positive voltage at the first terminal with respect to the secondterminal and not conducting in response to the positive voltage at thesecond terminal with respect to the first terminal.
 35. A circuit as inclaim 34, wherein the first, second, and third devices are formed at aface of a first semiconductor region having a first conductivity type.36. A circuit as in claim 35, wherein the first semiconductor region issurrounded on all sides by a second semiconductor region having a secondconductivity type.
 37. A circuit as in claim 35, wherein the firstsemiconductor region is enclosed on all sides and below by a secondsemiconductor region having a second conductivity type, and wherein thesecond semiconductor region is formed in a third region isolated fromthe first region.
 38. A circuit as in claim 34, wherein the first deviceis an MOS transistor.
 39. A circuit as in claim 38, wherein the MOStransistor comprises a control terminal coupled to the third terminal.40. A circuit as in claim 34, wherein the current path of the seconddevice is coupled between the first and third terminals by a firstresistor and the current path of the third device is coupled between thesecond and third terminals by a second resistor.
 41. A circuit as inclaim 34, wherein each of the first, second, and third devices comprisesa bulk terminal coupled to the third terminal.
 42. A circuit as in claim34, wherein the first device is a bipolar transistor.
 43. A circuit asin claim 42, wherein the bipolar transistor comprises a control terminalcoupled to the third terminal.
 44. A circuit as in claim 43, wherein thecurrent path of the second device is coupled between the first and thirdterminals by a first resistor and the current path of the third deviceis coupled between the second and third terminals by a second resistor.45. A circuit as in claim 34, wherein the first device comprises aplurality of parallel elongate semiconductor regions having a firstconductivity type, and wherein the current path of the first devicecomprises a plurality of semiconductor regions having a secondconductivity type formed between respective said semiconductor regionshaving the first conductivity type.